Staff Physical Design Engineer

Accountabilities:

• • Lead block-level and top-level physical design activities, including floorplanning, placement, clock tree synthesis, and routing.
  • Drive designs toward aggressive performance, power, and area (PPA) targets through advanced timing closure techniques.
  • Analyze and resolve power integrity challenges, including electromigration (EM), IR drop, and power grid verification.
  • Develop and maintain Tcl and Python automation scripts to improve physical design flows, methodologies, and engineering efficiency.
  • Work closely with physical verification teams to ensure designs meet applicable rules and implementation requirements.
  • Collaborate with foundry teams to address physical design requirements and support successful tapeout execution.
  • Contribute to physical design methodology development, flow setup, and evaluation of advanced implementation approaches.
  • Provide technical leadership on complex physical implementation challenges and help drive designs through the complete development lifecycle.

  Requirements:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
  • 10–15 years of dedicated professional experience in semiconductor physical design.
  • Extensive experience with EDA implementation flows, particularly Cadence design tools.
  • Strong understanding of static timing analysis (STA) and advanced timing closure methodologies.
  • Proven experience delivering both block-level and top-level physical designs; hierarchical floorplanning experience is a strong advantage.
  • Solid knowledge of low-power design techniques, physical debugging, EM/IR analysis, and power grid verification.
  • Strong scripting capabilities in Tcl or Python for design flow automation.
  • Understanding of advanced semiconductor process nodes and physical verification requirements associated with routing and implementation.
  • Experience establishing and evaluating physical design methodologies and implementation flows.
  • Familiarity with PDK management and semiconductor foundry tapeout processes is highly desirable.
  • Strong analytical, problem-solving, communication, and cross-functional collaboration skills.

  Benefits:

  • Remote opportunity available across the United States and Canada.
  • Annual salary range of $170,000–$240,000 USD for U.S.-based employees.
  • Annual salary range of $170,000–$230,000 CAD for Canada-based employees.
  • Actual compensation is determined based on job-related knowledge, skills, and experience.
  • Opportunity to work on advanced semiconductor technologies and next-generation AI computing systems.
  • High-impact technical role with significant ownership across physical implementation and tapeout activities.