Staff DFT Engineer

The Opportunity

We are looking for a high-energy, Staff-level DFT Engineer to join our silicon team. In the fast-paced world of Edge AI, efficiency is everything. As a "go-getter" in a startup environment, you’ll have the autonomy to shape the end-to-end DFT insertion process for our next-generation AI accelerators.

Key Responsibilities

• End-to-End DFT Strategy: Define and implement the complete DFT architecture as independent as possible, including Scan, MBIST, BSCAN, and Boundary Scan.
• Constraint Management: Take charge of DFT constraint development and management, ensuring seamless integration with synthesis and STA (Static Timing Analysis) teams.
• ATPG & Simulation: Generate high-coverage test patterns (Stuck-at, At-speed, Transition, Path Delay) and lead the verification of these patterns through timing-annotated simulations.
• AI-Specific Optimization: Implement advanced DFT techniques tailored for Edge AI architectures, such as high-bandwidth memory testing and low-power test modes.
• Hierarchical DFT: Design and execute hierarchical DFT flows to manage complexity in large-scale AI SOCs.
• Silicon Bring-up: Partner with the ATE (Automated Test Equipment) teams to debug patterns on silicon and drive yield improvement initiatives.

What You Bring

• The Experience: 9–10 years of hands-on experience in DFT, preferably with at least one full tape-out cycle in a lead or staff capacity.
• The Toolkit: Expert-level proficiency with industry-standard tools (e.g., Siemens Tessent, Synopsys DFTMAX/TetraMAX, or Cadence Genus/Modus).
• Technical Depth: Deep understanding of DFT-centric STA, power-aware DFT, and high-speed IO testing.
• Startup Mindset: You are comfortable wearing multiple hats. You don't wait for a manual; you build the manual.
• Edge AI Interest: A genuine interest in how AI hardware differs from general-purpose CPUs/GPUs.

Why Join Us?

• High Impact: In a startup, your decisions aren't buried in layers of bureaucracy; they are visible in the final silicon.