Senior ASIC Ethernet Design Engineer

Headquarters: Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions. We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles . Cornelis Networks is hiring talented Sr. ASIC Design Engineers with deep experience in one or more of the key areas required to build the world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions. A good candidate will have 15+ years of ASIC design experience, with 10+ years of relevant experience in networking hardware design, proven expertise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking. Key Responsibilities: End-to-end SoC/ASIC development. Front-end standard cell ASIC development including RTL development, Design Verification, synthesis, and post-silicon validation. Cross-functional collaboration and partnering with internal and external cross-functional teams, across all levels of the corporation. Define, implement, debug, and deliver system solutions around purpose-built ASICs. Pr