Principal ASIC Package Design Engineer

The Role

We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role owns the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.

Responsibilities

• Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy.
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.