PCIe ASIC Design Engineer

Headquarters: Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions. We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. Cornelis Networks is hiring a S enior ASIC Design Engineer to lead the design and integration of PCIe controllers into our next-generation SoCs. The ideal candidate will have deep expertise in PCI Express protocol (Gen4/Gen5/Gen6) , integration into high performance ASICs, emulation and post silicon bring - up. Key Responsibilities: Own end-to-end integration of PCIe IP into complex ASIC designs. Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems. Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency. Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability. Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams. Debug functional and performance issues at RTL, gate-level, and silicon. Ensure compliance with PCIe specificat