Design Verification Lead

Accountabilities:

• • Define and drive the overall verification architecture for complex SoCs, ensuring scalable methodologies from IP and block level through subsystem and full-chip verification.
  • Architect reusable, modular, and portable verification platforms that can support multiple chip programs and tape-outs.
  • Establish verification reuse and portability strategies, including Portable Stimulus (PSS)-based flows and cross-level stimulus reuse.
  • Lead the development of high-performance, coverage-driven testbenches using industry-standard methodologies such as UVM.
  • Develop and implement multi-level verification strategies covering individual blocks, multi-block subsystems, and complete SoCs.
  • Define verification quality metrics, coverage targets, closure strategies, and sign-off criteria to ensure consistent quality across programs.
  • Champion a fail-fast approach that identifies defects early, reduces verification risk, and improves overall design quality.
  • Drive initiatives aimed at first-pass silicon success while minimizing design escapes and post-silicon debugging requirements.
  • Explore and implement AI/ML techniques and AI agents to automate testbench generation, improve stimulus generation, accelerate coverage closure, optimize regressions, and enhance debug productivity.
  • Develop intelligent verification QA and anomaly-detection capabilities to improve the efficiency and effectiveness of verification workflows.
  • Partner closely with architecture, design, physical design, and software teams to identify issues early and ensure alignment across the complete SoC development lifecycle.
  • Mentor and guide verification engineers on methodologies, best practices, architectural decisions, automation, and reusable verification frameworks.
  • Establish verification frameworks and processes that improve reuse across programs and reduce overall verification cycle time.

  Requirements:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
  • 10+ years of professional experience in Design Verification, including significant experience verifying complex, large-scale SoCs.
  • Proven experience defining and deploying verification architectures for sophisticated semiconductor designs.
  • Strong hands-on expertise with SystemVerilog and UVM.
  • Deep knowledge of coverage-driven verification, including functional and code coverage, coverage analysis, and closure.
  • Strong experience with assertion-based verification and SystemVerilog Assertions (SVA).
  • Hands-on experience with Portable Stimulus (PSS) and reusable, cross-level stimulus methodologies.
  • Experience verifying industry-standard protocols such as PCIe, DDR, Ethernet, CXL, and/or UCIe.
  • Strong understanding of SoC architectures targeting AI, HPC, networking, or similarly demanding compute environments.
  • Experience handling multi-IP integration challenges, coherency, high-speed interfaces, and large-scale data movement.
  • Strong system-level debugging capabilities and the ability to investigate complex verification and integration issues.
  • Demonstrated architectural thinking and a systems-level approach to verification.
  • Strong ownership, quality focus, and bias toward automation, scalability, and reuse.
  • Excellent technical leadership, mentoring, communication, and cross-functional collaboration skills.
  • Ability to operate effectively in a fast-paced environment with a fail-fast, learn-fast mindset.
  • Experience applying AI/ML to verification workflows is a strong advantage.
  • Exposure to emulation, prototyping, hybrid verification platforms, performance verification, or power-aware verification is desirable.
  • Experience developing verification frameworks reused across multiple tape-outs is a plus.

  Benefits:

  • Remote-friendly working model within India.
  • Opportunity to work on advanced semiconductor technologies for AI, HPC, and networking infrastructure.
  • High level of technical ownership and influence over verification architecture and methodology.
  • Opportunity to build reusable verification platforms supporting multiple silicon programs.
  • Exposure to emerging AI-driven verification, automation, and intelligent testing techniques.
  • Collaboration with experienced semiconductor engineers across global teams.
  • Fast-moving environment with minimal bureaucracy and strong emphasis on technical execution.
  • Opportunity to contribute directly to real silicon products and mission-critical AI infrastructure.
  • Strong emphasis on ownership, deep technical expertise, innovation, and high engineering standards.
  • Significant opportunity for professional growth while helping establish and scale a world-class engineering organization in India.
  • Compensation and additional benefits are determined by the hiring organization and may vary based on employment arrangements.