Principal Verification Engineer (Remote)

Responsibilities

• Lead verification planning and execution at the block and full-chip level.
• Partner with architects and designers to align verification goals with design intent.
• Build, enhance, and maintain UVM-based verification environments.
• Achieve and track coverage metrics to ensure complete functional validation.
• Collaborate with lab teams for silicon bring-up and debug.
• Drive verification methodology improvements and mentor team members.

Qualifications

• MSEE with 10+ years or PhD with 7+ years of verification experience.
• Advanced knowledge of SystemVerilog and UVM methodology.
• Proficiency in EDA tools such as VCS, Xcelium, and IMC.
• Strong scripting and automation skills (Python, Perl).
• Excellent communication and leadership across cross-functional teams.

Preferred / Plus

• Understanding of SVA and regression management tools (e.g., Jenkins).